The present invention relates to a solid-state image sensor and an image reading method, more specifically a solid-state image sensor having 4-Tr-pixels and an image reading method for the solid-state image sensor.
Solid-state image sensors basically formed of CMOS generally use the structure called APS (Active Pixel Sensor), which comprises photodiodes for converting optical signals to electric signals, reset transistors for resetting the photodiodes, source follower transistors for converting signal charges of the photodiodes to voltages to output the signal charges in voltage, and select transistors for connecting/selecting pixels and signal lines. Solid-state image sensors formed of the above-described three kinds of transistors, the so-called 3-Tr-pixel solid-state image sensors are described in, e.g., Reference 1 (Japanese published unexamined patent application No. 2002-077731), etc.
It is said that the solid-state image sensors having 3-Tr-pixels are vulnerable to noises due to thermal noises (kTC noises). The structure called 4-Tr-pixel which can remove even the kTC noises has been proposed. The solid-state image sensor having 4-Tr-pixels has the structure further comprising transfer transistors (transfer gates) between the reset transistors and the photodiodes, and an n-type diffused layer (FD: Floating Diffusion) between the reset transistors and the transfer transistors is connected to the gates of the source follower transistors. The solid-state image sensors having the 4-Tr-pixels are described in, e.g., Reference 2 (Japanese published unexamined patent application No. 2000-201300), Reference 3 (Japanese published unexamined patent application No. 2000-260971), and Reference 4 (Japanese published unexamined patent application No. 2001-177765). Solid-state image sensors having other pixel structures are described in, e.g., Reference 5 (Japanese published unexamined patent application No. 2000-152086) and Reference 6 (Specification of U.S. Pat. No. 6,005,619).
FIG. 62 is a circuit diagram of the solid-state image sensor having 4-Tr-pixels. In FIG. 62, a pixel array unit 100 is represented by 2×2 unit pixels.
Each pixel is formed of a photodiode PD, a transfer transistor TG, a reset transistor RST, a source follower transistor SF-Tr, and a select transistor SELECT.
The cathode terminal of the photodiode PD is connected to the source terminal of the transfer transistor TG. The anode terminal of the photodiode PD is grounded. The drain terminal of the transfer transistor TG is connected to the source terminal of the reset transistor RST and the gate terminal of the source follower transistor SF-Tr. An impurity diffused region which stores charges transferred from the photodiode PD is present in the region where the drain terminal of the transfer transistor TG is connected to the source terminal of the reset transistor RST and the gate terminal of the source follower transistor SF-Tr. The impurity diffused region will be hereinafter called a floating diffusion FD. The source terminal of the source follower transistor SF-Tr is connected to the drain terminal of the select transistor SELECT.
The respective pixels adjacent to each other in the row direction are connected to a transfer gate (TG) line which commonly connects the gate terminals of the transfer transistors TG, to a reset (RST) line which commonly connects the gate terminals of the reset transistors RST, and to a select line which commonly connects the gate terminals of the select transistor SELECT.
The respective pixels adjacent to each other in the column direction are connected to a signal read line which commonly connects the source terminals of the select transistors SELECT and to a VR (reset voltage) line which commonly connects the drain terminals of the reset transistors RST and the drain terminals of the source follower transistors SF-Tr.
The TG lines, the RST lines and the select lines are connected to a row selecting circuit 102. The signal read lines are connected to a signal read/noise canceller circuit 104. The signal read/noise canceller circuit 104 is connected to an output circuit 108 via an AD converter 106. The VR lines are connected to an electric power source whose voltage is substantially a source voltage or an electric power source whose voltage is decreased in the chip.
Then, the image reading method of the solid-state image sensor shown in FIG. 62 will be explained with reference to FIG. 63. FIG. 63 is a timing chart explaining the image reading method of the solid-state image sensor. Positive voltages are taken on the vertical axis, and time is taken on the horizontal axis.
In the reset state, the photodiode PD has a prescribed reference voltage reflecting a reset voltage VR. When light is incident on the photodiode PD, electrons are generated, and the voltage of the photodiode PD is gradually decreased.
Then, when the reset signal is applied to the RST line, the floating diffusions FD are reset, and voltage of the floating diffusions FD is stabilized at a prescribed value. This voltage is applied to the gate terminal of the source follower transistor SF-Tr. In this state, the select signal is applied to the select line, and a voltage corresponding to the reset voltage VR−the threshold voltage Vth is outputted to the signal read line (VR read).
Next, a signal is applied to the TG line to turn on the transfer transistor TG, and the electrons stored in the photodiode PD are transferred to the floating diffusion FD. Thus, the voltage of the floating diffusion FD is lowered while potential of the photodiode PD becomes said reference voltage.
The voltage of the floating diffusion FD is lowered to thereby lower voltage to be applied to the gate terminal of the source follower transistor SF-Tr. In this state, when a select signal is again applied to the select line, a voltage decreased by voltage change amounts ΔV corresponding to electron amounts stored in the photodiode PD, i.e., the reset voltage VR−the threshold voltage Vth−the voltage change amounts ΔV is outputted to the signal read line (Vsignal read).
Next, difference between the VR read voltage (VR−Vth) and the Vsignal read voltage (VR−Vth−ΔV) is given by the signal read/noise canceller circuit 102 to thereby give the voltage change amounts ΔV. Thus, output voltage variations of the source follower transistors SF-Tr of the respective pixels due to the threshold voltage variations are cancelled, and voltage variation amounts ΔV corresponding to the electron amounts stored in the photodiodes PD can be correctly read.
A string of the reading operations described above is made sequentially on the respective pixels, and optical signals detected by the photodiodes PD can be read.
The solid-state image sensor having 4-Tr-pixels, which has more constituent elements than the solid-state image sensor having 3-Tr-pixels has risks of lower yields, etc. An area occupied by the photodiode PD in a pixel is decreased. From these viewpoints, Reference 4 proposes that signal lines are commonly used by adjacent pixels. In Reference 4, the RST line and the select line, the RST line and the TG line, or the TG line and the select line are commonly used by adjacent pixels for a decreased number of lines and higher yields.
However, Reference 4 neither teaches nor suggests a specific layout of pixels. In the above-described image reading method, charges from the photodiode PD of each row are transferred to the floating diffusion FD and read. This operation is made sequentially for the other rows, which often causes “deflections” and “distortions” due to detection time lags among the rows.